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e december 1996 order number: 290533-004 n 85 ns access time (t rac ) ? supports both standard and fast- page-mode accesses n multiplexed address bus ? ras# and cas# control inputs n no-glue interface to many memory controllers n smartvoltage technology ? user-selectable 3.3v or 5v v cc ? user-selectable 5v or 12v v pp n 0.33 mb/sec write transfer rate n x16 architecture n 56-lead tsop type i package n backwards-compatible with 28f008sa command set n 2 a typical deep power-down current n 1 ma typical i cc active current in static mode n 32 separately-erasable/lockable 64-kbyte blocks n 1 million erase cycles per block n state-of-the-art 0.6 m etox? iv flash technology intels 28f016xd 16-mbit flash memory is a revolutionary architecture which is the ideal choice for designing truly revolutionary high-performance products. combining its dram-like read performance and interface with the intrinsic nonvolatility of flash memory, the 28f016xd eliminates the traditional redundant memory paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory, such as dram, for improved system performance. the i nnovative capabilities of the 28f016xd enable the design of direct-execute code and mass storage data/file flash memory systems. the 28f016xds dram-like interface with a multiplexed address bus, flexible v cc and v pp voltages, power saving features, extended cycling, fast program and read performance, symmetrically-blocked architecture, and selective block locking provide a highly flexible memory component suitable for resident flash component arrays on the system board or simms. the dram-like interface with ras# and cas# control inputs allows for easy migration to flash memory in existing dram-based systems. the 28f 016xds dual read voltage allows the same component to operate at either 3.3v or 5.0v v cc . programming voltage at 5.0v v pp minimizes external circuitry in minimal-chip, space critical designs, while the 12.0v v pp option maximizes program/erase performance. the x16 architecture allows optimization of the memory-to-processor interface. its high read performance combined with flexible block locking enable both storage and execution of operating systems/ application software and fast access to large data tables. the 28f016xd is manufactured on intels 0.6 m etox iv process technology. 28f016xd 16-mbit (1 mbit x 16) dram-interface flash memory
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f016xd may contain design defects or errors known as errata. current characterized errata are available upon request. *third-party brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683 copyright ? intel corporation, 1996 cg-041493
e 28f016xd flash memory 3 contents page page 1.0 introduction ......................................... 5 1.1 product overview...................................... 5 2.0 device pinout......................................... 6 2.1 lead descriptions ..................................... 9 3.0 memory maps ....................................... 11 3.1 extended status registers memory map ........................................ 12 4.0 bus operations, commands and status register definitions.......... 13 4.1 bus operations ....................................... 13 4.2 28f008sacompatible mode command bus definitions.................... 14 4.3 28f016xdenhanced command bus definitions ..................................... 15 4.4 compatible status register .................... 16 4.5 global status register ............................ 17 4.6 block status register.............................. 18 5.0 electrical specifications ............. 19 5.1 absolute maximum ratings..................... 19 5.2 capacitance............................................ 20 5.3 transient input/output reference waveforms........................................... 21 5.4 dc characteristics (v cc = 3.3v 0.3v).............................. 22 5.5 dc characteristics (v cc = 5.0v 0.5v).............................. 25 5.6 ac characteristics (v cc = 3.3v 0.3v)..............................28 read, write, read-modify-write and refresh cycles (common parameters) ....28 read cycle...............................................28 write cycle ...............................................29 read-modify-write cycle..........................30 fast page mode cycle .............................30 fast page mode read-modify-write cycle ........................................................30 refresh cycle...........................................31 misc. specifications ..................................31 5.7 ac characteristics (v cc = 5.0v 0.5v)..............................33 read, write, read-modify-write and refresh cycles (common parameters) ....33 read cycle...............................................34 write cycle ...............................................35 read-modify-write cycle..........................35 fast page mode cycle .............................35 fast page mode read-modify-write cycle ........................................................36 refresh cycle...........................................36 misc. specifications ..................................37 5.8 ac waveforms ........................................38 5.9 power-up and reset timings..................50 5.10 erase and word program performance ..51 6.0 mechanical specifications ............52 appendix a: device nomenclature and ordering information .....................................53 appendix b: additional information...............54
28f016xd flash memory e 4 revision history number description -001 original version -002 removed support of the following features: all page buffer operations (read, write, programming, upload device information) command queuing software sleep and abort erase all unlocked blocks device configuration command changed definition of nc. removed no internal connection to die from description. added xx to upper byte of command (data) definition in sections 4.2 and 4.3. modified parameters v and i of section 5.1 to apply to nc pins. increased i pps (v pp read current) for v pp > v cc to 200 a at v cc = 3.3v/5.0v. changed v cc = 5.0v dc characteristics (section 5.5) marked with note 1 to indicate that these currents are specified for a cmos rise/fall time (10% to 90%) of <5 ns and a ttl rise/fall time of <10 ns. corrected rp# high to ras# going low to be a min specification at v cc = 3.3v/5.0v. increased typical word/block program times (t whrh1 /t whrh3 ) for v pp = 5.0v: t whrh1 from 24.0 s to 35.0 s and t whrh3 from 0.8 sec to 1.2 sec at v cc = 3.3v t whrh1 from 16.0 s to 25.0 s and t whrh3 from 0.6 sec to 0.85 sec at v cc = 5.0v changed time from erase suspend command to wsm ready spec name to erase suspend latency time to read; modified typical values and added min/max values at v cc =3.3/5.0v and v pp =5.0/12.0v (section 5.10). minor cosmetic changes throughout document. -003 added 3/5# pin to pinout configuration (figure 2), product overview (section 1.1) and lead descriptions (section 2.1) modified block diagram (figure 1): removed address/data queues, page buffers, and address counter; added 3/5# pin added 3/5# pin to test conditions of i cc 2 and i cc 5 specifications modified power-up and reset timings (section 5.9) to include 3/5# pin: removed t 5vph and t 3vph specifications; added t plyl , t plyh , t ylph , and t yhph specifications corrected tsop mechanical specification a1 from 0.50 mm to 0.050 mm (section 6.0) minor cosmetic changes throughout document. -004 updated dc specifications i cc 3, i cc 4, i cc 6, i cc 7, i ccd and i ppes updated ac specifications t cas (min), t rcd (max) and t cwd (min)
e 28f016xd flash memory 5 1.0 introduction the documentation of the intel 28f016xd flash memory device includes this datasheet, a detailed users manual, and a number of application notes and design tools, all of which are referenced in appendix b. the datasheet is intended to give an overview of the chip feature-set and of the operating ac/dc specifications. the 16-mbit flash product family users manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. it also contains the full list of software algorithm flowcharts, and a brief section on compatibility with the intel 28f008sa. significant 28f016xd feature revisions occurred between datasheet revisions 290533-001 and 290533-002. these revisions center around removal of the following features: all page buffer operations (read, write, programming, upload device information) command queuing software sleep and abort erase all unlocked blocks device configuration command in addition, a significant 28f016xd change occurred between datasheet revisions 290532-002 and 290532-003. this change centers around the addition of a 3/5# pin to the devices pinout configuration. figure 2 shows the 3/5# pin assignment for the tsop type 1 package. intel recommends that all customers obtain the latest revisions of 28f016xd documentation. 1.1 product overview the 28f016xd is a high-performance, 16-mbit (16,777,216-bit) block erasable, nonvolatile random access memory, organized as 1 mword x 16. the 28f016xd includes thirty-two 32-kw (32,768 word) blo cks. a chip memory map is shown in figure 3. the implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and result in greater product reliability and ease-of-use as compared to other flash memories. significant features of the 28f016xd include: no-glue interface to memory controllers improved word program performance smartvoltage technology ? selectable 3.3v or 5.0v v cc ? selectable 5.0v or 12.0v v pp block program/erase protection the 28f016xd's multiplexed address bus with ras# and cas# inputs allows for a no glue interface to many existing in-system memory controllers. as such, 28f016xd-based simms (72-pin jedec standard) offer attractive advantages over their dram counterparts in many applications. for more information on 28f016xd- based simm designs, see the application note referenced at the end of this datasheet. the 28f016xd incorporates smartvoltage technology, providing v cc operation at both 3.3v and 5.0v and program and erase capability at v pp = 12.0v or 5.0v. operating at v cc = 3.3v, the 28f016xd consumes less than 60% of the power consumption at 5.0v v cc , while 5.0v v cc provides the highest read performance capability. v pp = 5.0v operation eliminates the need for a separate 12.0v converter, while v pp = 12.0v maximizes program/erase performance. in addition to the flexible program and erase voltages, the dedicated v pp gives complete code protection with v pp v pplk . a 3/5# input pin configures the devices internal circuitry for optimal 3.3v or 5.0v read/program operation. a command user interface (cui) serves as the system interface betw een the microprocessor or microcontroller and the internal memory operation. internal algorithm automation allows word programs and block erase operations to be executed using a two-write command sequence to the cui in the same way as the 28f008sa 8- mbit flashfile? memory. software locking of memory blocks is an added feature of the 28f016xd as compared to the 28f008sa. the 28f016xd provides selectable block locking to protect code or data such as direct-executable operating systems or application code. each block has an associated nonvolatile lock-bit which determines the lock status of the
28f016xd flash memory e 6 block. in addition, the 28f016xd has a master write protect pin (wp#) which prevents any modifications to memory blocks whose lock-bits are set. writing of memory data is performed in word increments typically within 6 s (12.0v v pp )a 33% improvement over the 28f008sa. a block erase operation erases one of the 32 blo cks in typically 0.6 sec (12.0v v pp ), independent of the other blocks, which is about a 65% improvement over the 28f008sa. each block can be written and erased a minimum of 100,000 cycles. systems can achieve one million block erase cycles by providing wear- leveling algorithms and graceful block retirement. these techniques have already been employed in many flash file systems and hard disk drive designs. all operations are started by a sequence of write commands to the device. three types of status registers (described in detail later in this datasheet) and a ry/by# output pin provide information on the progress of the requested operation. the following status registers are used to provide device and wsm information to the user : a compatible status register (csr) which is 100% compatible with the 28f008sa flashfile memory status register. the csr, when used alone, provides a straightforward upgrade capability to the 28f016xd from a 28f008sa- based design. a global status register (gsr) which also informs the system of overall write state machine (wsm) status. 32 block status registers (bsrs) which provide block-specific status information such as the block lock-bit status. the gsr and bsr memory maps are shown in figure 4. the 28f016xd incorporates an open drain ry/by# output pin. this feature allows the user to or-tie many ry/by# pins together in a multiple memory configuration such as a resident flash array. the 28f016xd is specified for a maximum fast page mode cycle time of 65 ns (t pc,r ) at 5.0v operation (4.75v to 5.25v) over the commercial temperature range (0 c to +70 c). a corresponding maximum fast page mode cycle time of 75 ns at 3.3v (3.0v to 3.6v and 0 c to +70 c) is achieved for reduced power consumption applications. the 28f016xd incorporates an automatic power saving (aps) feature, which substantially reduces the active current when the device is in static mode of operation (addresses not switching). in aps mode, the typical i cc current is 1 ma at 5.0v (3.0 ma at 3.3v). a deep power-down mode of operation is invoked when the rp# (called pwd# on the 28f008sa) pin transitions low. this mode brings the device power consumption to less than 2.0 a, typically, and provides additional write protection by acting as a device reset pin during power transitions. a reset time of 300 ns (5.0v v cc operation) is required from rp# switching high until dropping ras#. in the deep power-down state, the wsm is reset (any current operation will abort) and the csr, gsr and bsr registers are cleared. a cmos standby mode of operation is enabled when ras# and cas# transition high and rp# stays high with all input control pins at cmos levels. in this mode, the device typically draws an i cc standby current of 70 a at 5.0v v cc . the 28f016xd is available in a 56-lead, 1.2 mm thick, 14 mm x 20 mm tsop type i package. this form factor and pinout allow for very high board layout densities. 2.0 device pinout the 28f016xd 56-lead tsop type i pinout configuration is shown in figure 2.
e 28f016xd flash memory 7 output buffer output buffer input buffer input buffer i/o logic id register csr esrs data comparator cui y decoder x decoder 64-kbyte block 0 64-kbyte block 1 64-kbyte block 30 64-kbyte block 31 wsm program/erase voltage switch address register input buffer/ address de-mux y gating/sensing output multiplexer gnd dq 8-15 dq 0-7 ras# cas# oe# we# wp# rp# v cc v ry/by# pp a 0-9 data register v cc ras# cas# 3/5# 0533_01 figure 1. 28f016xd block diagram architectural evolution includes multiplexed address bus, smartvoltage technology, and extended registers
28f016xd flash memory e 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 3/5# gnd nc a a a a a v ras# cas# 29 30 31 32 33 34 56 55 53 54 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 nc nc gnd v rp# nc nc nc nc gnd nc nc a a a a a wp# we# oe# ry/by# dq dq dq dq gnd dq dq dq dq v gnd dq dq dq dq v dq dq dq dq nc nc nc 9 8 7 6 5 cc pp 15 7 14 6 13 5 12 4 cc 11 3 10 2 cc 9 1 8 e28f016xd 56-lead tsop pinout 14 mm x 20 mm top view 0 v cc 4 3 2 1 0 0533_02 figure 2. 28f016xd 56-lead tsop type i pinout configuration
e 28f016xd flash memory 9 2.1 lead descriptions symbol type name and function a 0 Ca 9 input multiplexed row/column addresses: selects a word within one of thirty-two 32-kword blocks. row (upper) addresses are latched on the falling edge of ras#, while column (lower) addresses are latched on the falling edge of cas#. dq 0 Cdq 15 input/output data bus: inputs data and commands during cui write cycles. outputs array, identifier or status data (dq 0-7 ) in the appropriate read mode. floated when the chip is de-selected or the outputs are disabled. ras# input row address strobe: latches row address information on inputs a 9 - 0 when ras# transitions low. a subsequent cas# low transition initiates 28f016xd read or program operations. cas# input column address strobe: latches column address information on inputs a 9 - 0 when cas# transitions low. when preceded by a ras# low transition, cas# low initiates 28f016xd read or program operations, along with oe# and we#. subsequent cas# low transitions, with ras# held low, enable fast page mode reads/programs rp# input reset/power-down: rp# low places the device in a deep power- down state. all circuits that consume static power, even those circuits enabled in standby mode, are turned off. when returning from deep power-down, a recovery time of 300 ns at 5.0v v cc is required to allow these circuits to power-up. when rp# goes low, the current wsm operation is terminated, and the device is reset. all status registers return to ready (with all status flags cleared). exit from deep power-down places the device in read array mode. oe# input output enable: gates device data through the output buffers when low in combination with ras# and cas# low. the outputs float to tri-state off when oe# is high. oe# can be tied to gnd if not controlled by the system memory controller. ras# and cas# high override oe# low. we# low also overrides oe# low. we# input write enable: controls access to the cui, data register and address register. we# is active low and initiates programs in combination with ras# and cas# low. we# low overrides oe# low. ras# and cas# high override we# low. ry/by# open drain output ready/busy: indicates status of the internal wsm. when low, it indicates that the wsm is busy performing an operation. ry/by# floating indicates that the wsm is ready for new operations, erase is suspended, or the device is in deep power-down mode. this output is always active (i.e., not floated to tri-state off when oe#, ras# or cas# are high). wp# input write protect: erase blocks can be locked by writing a nonvolatile lock-bit for each block. when wp# is low, those locked blocks as reflected by the block-lock status bits (bsr.6), are protected from inadvertent data programs or erases. when wp# is high, all blocks can be written or erased regardless of the state of the lock-bits. the wp# input buffer is disabled when rp# transitions low (deep power-down mode).
28f016xd flash memory e 10 2.1 lead descriptions (continued) symbol type name and function 3/5# input 3.3/5.0 volt select: 3/5# high configures internal circuits for 3.3v operation. 3/5# low configures internal circuits for 5.0v operation. note: reading the array with 3/5# high in a 5.0v system could damage the device. reference the power-up and reset timings (section 5.9) for 3/5# switching delay to valid data. v pp supply program/erase power supply (12.0v 0.6v, 5.0v 0.5v): for erasing memory array blocks or writing words into the flash array. v pp = 5.0v 0.5v eliminates the need for a 12.0v converter, while connection to 12.0v 0.6v maximizes program/erase performance. note: successful completion of program and erase attempts is inhibited with v pp at or below 1.5v. program and erase attempts with v pp between 1.5v and 4.5v, between 5.5v and 11.4v, and above 12.6v produce spurious results and should not be attempted. v cc supply device power supply (3.3v 0.3v, 5.0v 0.5v): to switch 3.3v to 5.0v (or vice versa), first ramp v cc down to gnd, and then power to the new v cc voltage. do not leave any power pins floating. gnd supply ground for all internal circuitry: do not leave any ground pins floating. nc no connect: lead may be driven or left floating.
e 28f016xd flash memory 11 3.0 memory maps 32-kword block fffff 31 f8000 f7fff f0000 effff e8000 e7fff e0000 dffff 30 29 28 27 d8000 d7fff d0000 cffff c8000 c7fff c0000 bffff 26 25 24 23 b8000 b7fff b0000 a8fff a8000 a7fff a0000 9ffff 22 21 20 19 98000 97fff 90000 8ffff 88000 87fff 80000 7ffff 18 17 16 15 78000 77fff 70000 6ffff 68000 67fff 60000 5ffff 14 13 12 11 58000 57fff 50000 4ffff 48000 47fff 40000 3ffff 10 9 8 7 38000 37fff 30000 2ffff 28000 27fff 20000 1ffff 6 5 4 3 18000 17fff 10000 0ffff 08000 07fff 00000 2 1 0 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block 32-kword block a [19-0] 0533_03 note: the upper 10 bits (a 19 C10 ) reflect 28f016xd addresses a 9C0 , latched by ras#. the lower 10 bits (a 9C0 ) reflect 28f016xd addresses a 9C0 , latched by cas#. figure 3. 28f016xd memory map
28f016xd flash memory e 12 3.1 extended status registers memory map reserved gsr reserved bsr0 00002h 00001h reserved reserved 00000h 00003h reserved 07fffh reserved gsr reserved bsr31 f8002h f8001h reserved reserved f8000h f8003h reserved fffffh a 19-0 0533_04 note: the upper 10 bits (a 19 C10 ) reflect 28f016xd addresses a 9C0 , latched by ras#. the lower 10 bits (a 9C0 ) reflect 28f016xd addresses a 9C0 , latched by cas#. figure 4. extended status registers memory map
e 28f016xd flash memory 13 4.0 bus operations, commands and status register definitions 4.1 bus operations mode notes rp# ras# cas# oe# we# dq 0 C15 ry/by# row address latch 1,2,9 v ih v ih xx x x column address latch 1,2,9 v ih v il xx x x read 1,2,7 v ih v il v il v il v ih d out x output disable 1,6,7 v ih v il v il v ih v ih high z x standby 1,6,7 v ih v ih v ih x x high z x deep power-down 1,3 v il xxxx high z v oh manufacturer id 4,8 v ih v il v il v il v ih 0089h v oh device id 4,8 v ih v il v il v il v ih 66a8h v oh write 1,5,6 v ih v il v il xv il d in x notes: 1. x can be v ih or v il for address or control pins except for ry/by#, which is either v ol or v oh , or high z or d out for data pins depending on whether or not oe# is active. 2. ry/by# output is open drain. when the wsm is ready, erase is suspended or the device is in deep power-down mode, ry/by# will be at v oh if it is tied to v cc through a resistor. ry/by# at v oh is independent of oe# while a wsm operation is in progress. 3. rp# at gnd 0.2v ensures the lowest deep power-down current. 4. a 0 (latched by cas#) at v il provides the manufacturer id code. a 0 (latched by cas#) at v ih provides the device id code. all other addresses (row and column) should be set to zero. 5. commands for erase, data program, or lock-block operations can only be completed successfully when v pp = v pph1 or v pp = v pph2 . 6. while the wsm is running, ry/by# stays at v ol until all operations are complete. ry/by# goes to v oh when the wsm is not busy or in erase suspend mode. 7. ry/by# may be at v ol while the wsm is busy performing various operations (for example, a status register read during a program operation). 8. the 28f016xd shares an identical device identifier with the 28f016xs. 9. row (upper) addresses are latched via inputs a 0-9 on the falling edge of ras#. column (lower) addresses are latched via inputs a 0-9 on the falling edge of cas#. row addresses must be latched before column addresses are latched.
28f016xd flash memory e 14 4.2 28f008sa compatible mode command bus definitions first bus cycle second bus cycle command notes oper addr data (4) oper addr data (4) read array write x xxffh read aa ad intelligent identifier 1 write x xx90h read ia id read compatible status register 2 write x xx70h read x csrd clear status register 3 write x xx50h word program write x xx40h write pa pd alternate word program write x xx10h write pa pd block erase/confirm write x xx20h write ba xxd0h erase suspend/resume write x xxb0h write x xxd0h address data aa = array address ad = array data ba = block address csrd = csr data ia = identifier address id = identifier data pa = program address pd = program data x = dont care notes: 1. following the intelligent identifier command, two read operations access the manufacturer and device signature codes. 2. the csr is automatically available after device enters data program, erase, or suspend operations. 3. clears csr.3, csr.4 and csr.5. also clears gsr.5 and all bsr.5, bsr.4 and bsr.2 bits. see status register definitions. 4. the upper byte of the data bus (d 8 C15 ) during command writes is a dont care.
e 28f016xd flash memory 15 4.3 28f016xd enhanced command bus definitions first bus cycle second bus cycle command notes oper addr data (3) oper addr data (3) read extended status register 1 write x xx71h read ra gsrd bsrd lock block/confirm write x xx77h write ba xxd0h upload status bits/confirm 2 write x xx97h write x xxd0h address data ba = block address ad = array data ra = extended register address bsrd = bsr data pa = program address gsrd = gsr data x = dont care notes: 1. ra can be the gsr address or any bsr address. see figure 4 for the extended status register memory map. 2. upon device power-up, all bsr lock-bits come up locked. the upload status bits command must be written to reflect the actual lock-bit status. 3. the upper byte of the data bus (d 8 C15 ) during command writes is a dont care.
28f016xd flash memory e 16 4.4 compatible status register wsms ess es dws vpps r r r 76543210 notes: csr.7 = write state machine status 1 = ready 0 = busy ry/by# output or wsms bit must be checked to determine completion of an operation (erase, erase suspend, or data program) before the appropriate status bit (ess, es or dws) is checked for success. csr.6 = erase-suspend status 1 = erase suspended 0 = erase in progress/completed csr.5 = erase status 1 = error in block erasure 0 = successful block erase if dws and es are set to 1 during an erase attempt, an improper command sequence was entered. clear the csr and attempt the operation again. csr.4 = data-write status 1 = error in data program 0 = data program successful csr.3 = v pp status 1 = v pp error detect, operation abort 0 = v pp ok the vpps bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm interrogates v pp s level only after the data program or erase command sequences have been entered, and informs the system if v pp has not been switched on. vpps is not guaranteed to report accurate feedback between v ppl k (max) and v pph1 (min), between v pph1 (max) and v pph2 (min) and above v pph2 (max). csr.2C0 = reserved for future enhancements these bits are reserved for future use; mask them out when polling the csr.
e 28f016xd flash memory 17 4.5 global status register wsms oss dos r r r r r 76543210 notes: gsr.7 = write state machine status 1 = ready 0 = busy ry/by# output or wsms bit must be checked to determine completion of an operation (block lock, suspend, upload status bits, erase or data program) before the appropriate status bit (oss or dos) is checked for success. gsr.6 = operation suspend status 1 = operation suspended 0 = operation in progress/completed gsr.5 = device operation status 1 = operation unsuccessful 0 = operation successful or currently running gsr.4 C0 = reserved for future enhancements these bits are reserved for future use; mask them out when polling the gsr.
28f016xd flash memory e 18 4.6 block status register bs bls bos r r vpps vppl r 76543210 notes: bsr.7 = block status 1 = ready 0 = busy ry/by# output or bs bit must be checked to determine completion of an operation (block lock, suspend, erase or data program) before the appropriate status bits (bos, bls) is checked for success. bsr.6 = block lock status 1 = block unlocked for program/erase 0 = block locked for program/erase bsr.5 = block operation status 1 = operation unsuccessful 0 = operation successful or currently running bsr.2 = v pp status 1 = v pp error detect, operation abort 0 = v pp ok bsr.1 = v pp level 1 = v pp detected at 5.0v 10% 0 = v pp detected at 12.0v 5% bsr.1 is not guaranteed to report accurate feedback between the v pph1 and v pph2 voltage ranges. programs and erases with v pp between v pplk (max) and v pph1 (min), between v pph1 (max) and v pph2 (min), and above v pph2 (max) produce spurious results and should not be attempted. bsr.1 was a reserved bit on the 28f016sa. bsr.4,3,0 = reserved for future enhancements these bits are reserved for future use; mask them out when polling the bsrs.
e 28f016xd flash memory 19 5.0 electrical specifications 5.1 absolute maximum ratings* temperature under bias .................... 0c to +80c storage temperature ...................C65c to +125c notice: this is a production datasheet. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. *warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. v cc = 3.3v 0.3v systems sym parameter notes min max units test conditions t a operating temperature, commercial 1 0 70 c ambient temperature v cc v cc with respect to gnd 2 C0.2 7.0 v v pp v pp supply voltage with respect to gnd 2,3 C0.2 14.0 v v voltage on any pin (except v cc ,v pp ) with respect to gnd 2,5 C0.5 v cc + 0.5 v i current into any non-supply pin 5 30 ma i out output short circuit current 4 100 ma v cc = 5.0v 0.5v systems sym parameter notes min max units test conditions t a operating temperature, commercial 1 0 70 c ambient temperature v cc v cc with respect to gnd 2 C0.2 7.0 v v pp v pp supply voltage with respect to gnd 2,3 C0.2 14.0 v v voltage on any pin (except v cc ,v pp ) with respect to gnd 2,5 C2.0 7.0 v i current into any non-supply pin 5 30 ma i out output short circuit current 4 100 ma notes: 1. operating temperature is for commercial product defined by this specification. 2. minimum dc voltage is C0.5v on input/output pins. during transitions, this level may undershoot to C2.0v for periods <20 ns. maximum dc voltage on input/output pins is v cc + 0.5v which, during transitions, may overshoot to v cc + 2.0v for periods <20 ns. 3. maximum dc voltage on v pp may overshoot to +14.0v for periods <20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. 5. this specification also applies to pins marked nc.
28f016xd flash memory e 20 5.2 capacitance for a 3.3v 0.3v system: sym parameter notes typ max units test conditions c in capacitance looking into an address/control pin 168pft a = +25 c, f = 1.0 mhz c out capacitance looking into an output pin 1 8 12 pf t a = +25 c, f = 1.0 mhz c load load capacitance driven by outputs for timing specifications 1,2 50 pf for 5.0v 0.5v system: sym parameter notes typ max units test conditions c in capacitance looking into an address/control pin 168pft a = +25 c, f = 1.0 mhz c out capacitance looking into an output pin 1 8 12 pf t a = +25 c, f = 1.0 mhz c load load capacitance driven by outputs for timing specifications 1,2 100 pf note: 1. sampled, not 100% tested. 2. to obtain ibis models for the 28f016xd, please contact your local intel/distribution sales office.
e 28f016xd flash memory 21 5.3 transient input/output reference waveforms test points input output 2.0 0.8 0.8 2.0 2.4 0.45 0533_05 ac test inputs are driven at v oh (2.4 vttl) for a logic 1 and v ol (0.45 vttl) for a logic 0. input timing begins at v ih (2.0 vttl) and v il (0.8 vttl). output timing ends at v ih and v il . input rise and fall times (10% to 90%) <10 ns. figure 5. transient input/output reference waveform for v cc = 5.0v 0.5v (1) test points input output 1.5 3.0 0.0 1.5 0533_06 ac test inputs are driven at 3.0v for a logic 1 and 0.0v for a logic 0. input timing begins, and output timing ends, at 1.5v. input rise and fall times (10% to 90%) <10 ns. figure 6. transient input/output reference waveform for v cc = 3.3v 0.3v (2) notes: 1. testing characteristics for 28f016xd-85. 2. testing characteristics for 28f016xd-95.
28f016xd flash memory e 22 5.4 dc characteristics v cc = 3.3v 0.3v, t a = 0c to +70c 3/5# = pin set high for 3.3v operations sym parameter notes min typ max unit test condition i cc 1v cc word read current 1,4,5 50 70 ma v cc = v cc max ras#, cas# = v il ras#, cas#, addr. cycling @ t rc = min i out = 0 ma inputs = ttl or cmos i cc 2v cc standby current 1,5 1 4 ma v cc = v cc max ras#, cas#, rp# = v ih wp#, 3/5# = v il or v ih i cc 3v cc ras#-only refresh current 1,5 50 80 ma v cc = v cc max cas# = v ih ras# = v il ras#, addr. cycling @ t rc = min inputs = ttl or cmos i cc 4v cc fast page mode word read current 1,4,5 40 70 ma v cc = v cc max ras#, cas# = v il cas#, addr. cycling @ t pc = min i out = 0 ma inputs = v il or v ih i cc 5v cc standby current 1,5 70 130 a v cc = v cc max ras# cas# rp# = v cc 0.2v wp#, 3/5# = v cc 0.2v or gnd 0.2v i cc 6v cc cas#-before- ras# refresh current 1,5 40 15 ma v cc = v cc max cas#, ras# = v il cas#, ras#, addr. cycling @ t rc = min inputs = ttl or cmos i cc 7v cc standby current (self refresh mode) 1,5 40 10 ma v cc = v cc max ras#, cas# = v il i out = 0 ma inputs = v il or v ih i li input load current 1 1 a v cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 a v cc = v cc max v out = v cc or gnd i ccd v cc deep power- down current 1 2 10 a rp# = gnd 0.2v
e 28f016xd flash memory 23 5.4 dc characteristics (continued) v cc = 3.3v 0.3v, t a = 0c to +70c 3/5# = pin set high for 3.3v operations sym parameter notes min typ max unit test condition i ccw v cc word program current 1,6 8 12 ma v pp = 12.0v 5% program in progress 817mav pp = 5.0v 10% program in progress i cce v cc block erase current 1,6 6 12 ma v pp = 12.0v 5% block erase in progress 917mav pp = 5.0v 10% block erase in progress i cces v cc erase suspend current 1,2 1 4 ma ras#, cas# = v ih block erase suspended i pps v pp standby/read 1 1 10 a v pp v cc current 30 200 a v pp > v cc i ppd v pp deep power- down current 1 0.2 5 a rp# = gnd 0.2v i ppw v pp word program current 1,6 10 15 ma v pp = 12.0v 5% program in progress 15 25 ma v pp = 5.0v 10% program in progress i ppe v pp block erase current 1,6 4 10 ma v pp = 12.0v 5% block erase in progress 14 20 ma v pp = 5.0v 10% block erase in progress i ppes v pp erase suspend current 1 30 200 a block erase suspended v il input low voltage 6 -0.3 0.8 v v ih input high voltage 6 2.0 v cc + 0.3 v v ol output low voltage 6 0.4 v v cc = v cc min i ol = 4.0 ma v oh1 output high voltage 6 2.4 v v cc = v cc min i oh = C2.0 ma v oh2 6v cc - 0.2 vv cc = v cc min i oh = C100 a v ppl k v pp erase/program lock voltage 3,6 0.0 1.5 v v pph 1v pp during program/ erase operations 3 4.5 5.0 5.5 v v pph 2v pp during program/ erase operations 3 11.4 12.0 12.6 v v lko v cc erase/program lock voltage 2.0 v
28f016xd flash memory e 24 notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 3.3v, v pp = 12.0v or 5.0v, t = +25 c. 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i cc1 /i cc4 . 3. block erases, word programs and lock block operations are inhibited when v pp = v pplk and not guaranteed in the ranges between v pplk(max) and v pph1(min) , between v pph1(max) and v pph2(min) , and above v pph2(max) . 4. automatic power saving (aps) reduces i cc1 and i cc4 to 3.0 ma typical in static operation. 5. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 6. sampled, but not 100% tested. guaranteed by design.
e 28f016xd flash memory 25 5.5 dc characteristics v cc = 5.0v 0.5v, t a = 0c to +70c 3/5# = pin set low for 5.0v operations sym parameter notes min typ max unit test condition i cc 1v cc word read current 1,4,5 90 120 ma v cc = v cc max ras#, cas# = v il ras#, cas#, addr. cycling @ t rc = min i out = 0 ma inputs = ttl or cmos i cc 2v cc standby current 1,5 2 4 ma v cc = v cc max ras#, cas#, rp# = v ih wp#, 3/5# = v il or v ih i cc 3v cc ras#-only refresh current 1,5 90 145 ma v cc = v cc max cas# = v ih ras# = v il ras#, addr. cycling @ t rc = min inputs = ttl or cmos i cc 4v cc fast page mode word read current 1,4,5 80 130 ma v cc = v cc max ras#, cas# = v il cas#, addr. cycling @ t pc = min i out = 0 ma inputs = v il or v ih i cc 5v cc standby current 1,5 70 130 a v cc = v cc max ras#,cas#,rp# = v cc 0.2v wp#, 3/5# = v cc 0.2v or gnd 0.2v i cc 6v cc cas#-before- ras# refresh current 1,5 50 15 ma v cc = v cc max cas#, ras# = v il cas#, ras#, addr. cycling @ t rc = min inputs = ttl or cmos i cc 7v cc standby current (self refresh mode) 1,5 50 10 ma v cc = v cc max ras#, cas# = v il i out = 0 ma inputs = v il or v ih i li input load current 1 1 a v cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 a v cc = v cc max v out = v cc or gnd i ccd v cc deep power-down current 1 2 10 a rp# = gnd 0.2v
28f016xd flash memory e 26 5.5 dc characteristics (continued) v cc = 5.0v 0.5v, t a = 0c to +70c 3/5# = pin set low for 5.0v operations sym parameter notes min typ max unit test condition i ccw v cc word program current 1,6 25 35 ma v pp = 12.0v 5% word program in progress 25 40 ma v pp = 5.0v 10% word program in progress i cce v cc block erase current 1,6 18 25 ma v pp = 12.0v 5% block erase in progress 20 30 ma v pp = 5.0v 10% block erase in progress i cces v cc erase suspend current 1,2 2 4 ma ras#, cas# = v ih block erase suspended i pps v pp standby/read 1 1 10 a v pp v cc current 30 200 a v pp > v cc i ppd v pp deep power-down current 1 0.2 5 a rp# = gnd 0.2v i ppw v pp word program current 1,6 7 12 ma v pp = 12.0v 5% word program in progress 17 22 ma v pp = 5.0v 10% word program in progress i ppe v pp block erase current 1,6 5 10 ma v pp = 12.0v 5% block erase in progress 16 20 ma v pp = 5.0v 10% block erase in progress i ppes v pp erase susp.current 1 30 200 a block erase suspended v il input low voltage 6 C0.5 0.8 v v ih input high voltage 6 2.0 v cc + 0.5 v v ol output low voltage 6 0.45 v v cc = v cc min i ol = 5.8 ma v oh1 output high voltage 6 0.85 v cc vv cc = v cc min i oh = C2.5 ma v oh2 6v cc ? 0.4 vv cc = v cc min i oh = C100 a v ppl k v pp erase/program lock voltage 3,6 0.0 1.5 v v pph 1v pp during program/erase operations 3 4.5 5.0 5.5 v v pph 2v pp during program/erase operations 3 11.4 12.0 12.6 v v lko v cc erase/program lock voltage 2.0 v
e 28f016xd flash memory 27 notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0v, v pp = 12.0v or 5.0v, t = +25 c. these currents are specified for a cmos rise/fall time (10% to 90%) of <5 ns and a ttl rise/fall time of <10 ns. 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i cc1 /i cc4 . 3. block erases, word programs and lock block operations are inhibited when v pp = v pplk and not guaranteed in the ranges between v pplk(max) and v pph1(min) , between v pph1(max) and v pph2(min) , and above v pph2(max) . 4. automatic power saving (aps) reduces i cc1 and i cc4 to 1 ma typical in static operation. 5. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 6. sampled, not 100% tested. guaranteed by design.
28f016xd flash memory e 28 5.6 ac characteristics (11) v cc = 3.3v 0.3v, t a = 0c to +70c read, program, read-modify-program and refresh cycles (common parameters) versions 28f016xd-95 units sym parameter notes min max t rp ras# precharge time 10 ns t cp cas# precharge time 15 ns t asr row address set-up time 9 0 ns t rah row address hold time 9 15 ns t asc column address set-up time 9 0 ns t cah column address hold time 9 20 ns t ar column address hold time referenced to ras# 3,9 35 ns t rad ras# to column address delay time 8,9 15 15 ns t crp cas# to ras# precharge time 10 ns t oed oe# to data delay 10 30 ns t dzo oe# delay time from data-in 10 0 ns t dzc cas# delay time from data-in 10 0 ns t t transition time (rise and fall) 10 2 4 ns read cycle versions 28f016xd-95 units sym parameter notes min max t rc(r) random read cycle time 105 ns t ras(r) ras# pulse width (reads) 95 ns t cas(r) cas# pulse width (reads) 45 ns t rcd(r) ras# to cas# delay time (reads) 1 15 50 ns t rsh(r) ras# hold time (reads) 30 ns t csh(r) cas# hold time (reads) 95 ns t rac access time from ras# 1,8 95 ns t cac access time from cas# 1,2 40 ns t aa access time from column address 8 75 ns t oea oe# access time 40 ns
e 28f016xd flash memory 29 read cycle (continued) versions 28f016xd-95 units sym parameter notes min max t roh ras# hold time referenced to oe# 40 ns t rcs read command setup time 5 ns t rch read command hold time referenced to cas# 6,10 0 ns t rrh read command hold time referenced to ras# 6,10 0 ns t ral column address to ras# lead time 9 15 ns t cal column address to cas# lead time 9 75 ns t clz cas# to output in low-z 0 ns t oh output data hold time 0 ns t oho output data hold time from oe# 0 ns t off output buffer turn-off delay 4 30 ns t oez output buffer turn off delay time from oe# 30 ns t cdd cas# to data-in delay time 30 ns write cycle versions 28f016xd-95 units sym parameter notes min max t rc(w) random write cycle time 90 ns t ras(w) ras# pulse width (writes) 80 ns t cas(w) cas# pulse width (writes) 65 ns t rcd(w) ras# to cas# delay time (writes) 1 15 15 ns t rsh(w) ras# hold time (writes) 65 ns t csh(w) cas# hold time (writes) 80 ns t wcs write command set-up time 5 0 ns t wch write command hold time 15 ns t wcr write command hold time referenced to ras# 3 30 ns t wp write command pulse width 15 ns t rwl write command to ras# lead time 65 ns t cwl write command to cas# lead time 65 ns t ds data-in set-up time 7,9 0 ns t dh data-in hold time 7,9 15 ns t dhr data-in hold time referenced to ras# 3,9 30 ns
28f016xd flash memory e 30 read-modify-write cycle versions 28f016xd-95 units sym parameter notes min max t rwc read-modify-write cycle time 10 200 ns t rwd ras# to we# delay time 5,10 125 ns t cwd cas# to we# delay time 5,10 75 ns t awd column address to we# delay time 5,9,10 105 ns t oeh oe# command hold time 10 15 ns fast page mode cycle versions 28f016xd-95 units sym parameter notes min max t pc(r) fast page mode cycle time (reads) 75 ns t pc(w) fast page mode cycle time (writes) 80 ns t rasp(r) ras# pulse width (reads) 95 ns t rasp(w) ras# pulse width (writes) 80 ns t cpa access time from cas# precharge 85 ns t cpw we# delay time from cas# precharge 10 0 ns t cprh(r) ras# hold time from cas# precharge (reads) 75 ns t cprh(w) ras# hold time from cas# precharge (writes) 80 ns fast page mode read-modify-write cycle versions 28f016xd-95 units sym parameter notes min max t prwc fast page mode read-modify-write cycle time 10 170 ns
e 28f016xd flash memory 31 refresh cycle versions 28f016xd-95 units sym parameter notes min max t csr cas# set-up time (cas#-before-ras# refresh) 10 10 ns t chr cas# hold time (cas#-before-ras# refresh) 10 10 ns t wrp we# setup time (cas#-before-ras# refresh) 10 10 ns t wrh we# hold time (cas#-before-ras# refresh) 10 10 ns t rpc ras# precharge to cas# hold time 10 10 ns t rass ras# pulse width (self-refresh mode) 10 0 ns t rps ras# precharge time (self-refresh mode) 10 10 ns t cpn cas# precharge time (self-refresh mode) 10 10 ns t chs cas# hold time (self-refresh mode) 10 0 ns refresh versions 28f016xd-95 units sym parameter notes min max t ref refresh period 10 ms misc. specifications versions 28f016xd-95 units parameter notes min max rp# high to ras# going low 10 480 ns rp# set-up to we# going low 10 480 ns v pp set-up to cas# high at end of write cycle 10 100 ns we# high to ry/by# going low 10 100 ns rp# hold from valid status register data and ry/by# high 10 0 ns v pp hold from valid status register data and ry/by# high 10 0 ns
28f016xd flash memory e 32 notes: 1. operation within the t rcd(max) limit insures that t rac(max) can be met. t rcd(max) is specified as a reference point. 2. assumes that t rcd 3 t rcd(max) . 3. t ar , t wcr , t dhr are referenced to t rad(max) . 4. t off(max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 5. t wcs , t rwd , t cwd and t awd are non restrictive operating parameters. they are included in the datasheet as electrical characteristics only. if t wcs 3 t wcs(min) the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. if t cwd 3 t cwd(min) , t rwd 3 t rwd(min) , t awd 3 t awd(min) , then the cycle is a read-write cycle and the data output will contain the data read from the selected address. if neither of the above conditions are satisfied, the condition of the data out is indeterminate. 6. either t rch or t rrh must be satisfied for a read cycle. 7. these parameters are referenced to the cas# leading edge in early write cycles and to the we# leading edge in read- write cycles. 8. operation within the t rad(max) limit ensures that t rac(max) can be met, t rad(max) is specified as a reference point only. if t rad is greater than the specified t rad(max) limit, then the access time is controlled by t aa . 9. refer to command definition tables for valid address and data values. 10. sampled, but not 100% tested. guaranteed by design. 11. see ac input/output reference waveforms for timing measurements.
e 28f016xd flash memory 33 5.7 ac characteristics (11) v cc = 5.0v 0.5v, t a = 0c to +70c read, write, read-modify-write and refresh cycles (common parameters) versions 28f016xd-85 units sym parameter notes min max t rp ras# precharge time 10 ns t cp cas# precharge time 15 ns t asr row address set-up time 9 0 ns t rah row address hold time 9 15 ns t asc column address set-up time 9 0 ns t cah column address hold time 9 20 ns t ar column address hold time referenced to ras# 3,9 35 ns t rad ras# to column address delay time 8,9 15 15 ns t crp cas# to ras# precharge time 10 ns t oed oe# to data delay 10 30 ns t dzo oe# delay time from data-in 10 0 ns t dzc cas# delay time from data-in 10 0 ns t t transition time (rise and fall) 10 2 4 ns
28f016xd flash memory e 34 read cycle versions 28f016xd-85 units sym parameter notes min max t rc(r) random read cycle time 95 ns t ras(r) ras# pulse width (reads) 85 ns t cas(r) cas# pulse width (reads) 35 ns t rcd(r) ras# to cas# delay time (reads) 1 15 50 ns t rsh(r) ras# hold time (reads) 30 ns t csh(r) cas# hold time (reads) 85 ns t rac access time from ras# 1,8 85 ns t cac access time from cas# 1,2 35 ns t aa access time from column address 8 65 ns t oea oe# access time 35 ns t roh ras# hold time referenced to oe# 35 ns t rcs read command setup time 5 ns t rch read command hold time referenced to cas# 6,10 0 ns t rrh read command hold time referenced to ras# 6,10 0 ns t ral column address to ras# lead time 9 15 ns t cal column address to cas# lead time 9 65 ns t clz cas# to output in low-z 10 0 ns t oh output data hold time 10 0 ns t oho output data hold time from oe# 10 0 ns t off output buffer turn-off delay 4,10 30 ns t oez output buffer turn off delay time from oe# 10 30 ns t cdd cas# to data-in delay time 10 30 ns
e 28f016xd flash memory 35 write cycle versions 28f016xd-85 units sym parameter notes min max t rc(w) random write cycle time 75 ns t ras(w) ras# pulse width (writes) 65 ns t cas(w) cas# pulse width (writes) 50 ns t rcd(w) ras# to cas# delay time (writes) 1 15 15 ns t rsh(w) ras# hold time (writes) 50 ns t csh(w) cas# hold time (writes) 65 ns t wcs write command set-up time 5 0 ns t wch write command hold time 15 ns t wcr write command hold time referenced to ras# 3 30 ns t wp write command pulse width 15 ns t rwl write command to ras# lead time 50 ns t cwl write command to cas# lead time 50 ns t ds data-in set-up time 7,9 0 ns t dh data-in hold time 7,9 15 ns t dhr data-in hold time referenced to ras# 3,9 30 ns read-modify-write cycle versions 28f016xd-85 units sym parameter notes min max t rwc read-modify-write cycle time 10 175 ns t rwd ras# to we# delay time 5,10 115 ns t cwd cas# to we# delay time 5,10 65 ns t awd column address to we# delay time 5,9,10 100 ns t oeh oe# command hold time 10 15 ns fast page mode cycle versions 28f016xd-85 units sym parameter notes min max t pc(r) fast page mode cycle time (reads) 65 ns t pc(w) fast page mode cycle time (writes) 65 ns
28f016xd flash memory e 36 fast page mode cycle continued versions 28f016xd-85 units sym parameter notes min max t rasp(r) ras# pulse width (reads) 85 ns t rasp(w) ras# pulse width (writes) 65 ns t cpa access time from cas# precharge 70 ns t cpw we# delay time from cas# precharge 10 0 ns t cprh(r) ras# hold time from cas# precharge (reads) 65 ns t cprh(w) ras# hold time from cas# precharge (writes) 65 ns fast page mode read-modify-write cycle versions 28f016xd-85 units sym parameter notes min max t prwc fast page mode read-modify-write cycle time 10 145 ns refresh cycle versions 28f016xd-85 units sym parameter notes min max t csr cas# set-up time (cas#-before-ras# refresh) 10 10 ns t chr cas# hold time (cas#-before-ras# refresh) 10 10 ns t wrp we# setup time (cas#-before-ras# refresh) 10 10 ns t wrh we# hold time (cas#-before-ras# refresh) 10 10 ns t rpc ras# precharge to cas# hold time 10 10 ns t rass ras# pulse width (self-refresh mode) 10 0 ns t rps ras# precharge time (self-refresh mode) 10 10 ns t cpn cas# precharge time (self-refresh mode) 10 10 ns t chs cas# hold time (self-refresh mode) 10 0 ns refresh versions 28f016xd-85 units sym parameter notes min max t ref refresh period 10 ms
e 28f016xd flash memory 37 misc. specifications versions 28f016xd-85 units parameter notes min max rp# high to ras# going low 10 300 ns rp# set-up to we# going low 10 300 ns v pp set-up to cas# high at end of write cycle 10 100 ns we# high to ry/by# going low 10 100 ns rp# hold from valid status register data and ry/by# high 10 0 ns v pp hold from valid status register data and ry/by# high 10 0 ns notes: 1. operation within the t rcd(max) limit insures that t rac(max) can be met. t rcd(max) is specified as a reference point. 2. assumes that t rcd 3 t rcd(max) . 3. t ar , t wcr , t dhr are referenced to t rad(max) . 4. t off(max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 5. t wcs , t rwd , t cwd and t awd are non restrictive operating parameters. they are included in the datasheet as electrical characteristics only. if t wcs 3 t wcs(min) the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. if t cwd 3 t cwd(min) , t rwd 3 t rwd(min) , t awd 3 t awd(min) , then the cycle is a read-write cycle and the data output will contain the data read from the selected address. if neither of the above conditions are satisfied, the condition of the data out is indeterminate. 6. either t rch or t rrh must be satisfied for a read cycle. 7. these parameters are referenced to the cas# leading edge in early write cycles and to the we# leading edge in read- write cycles. 8. operation within the t rad(max) limit ensures that t rac(max) can be met, t rad(max) is specified as a reference point only. if t rad is greater than the specified t rad(max) limit, then the access time is controlled by t aa . 9. refer to command definition tables for valid address and data values. 10. sampled, but not 100% tested. guaranteed by design. 11. see ac input/output reference waveforms for timing measurements.
28f016xd flash memory e 38 5.8 ac waveforms : don't care t rc t ras t rp t csh t rcd t cas t rsh column row t t ras# cas# address we# t rcs din oe# dout dout open t oed t cdd t rch t rrh t asc t rah t asr t cah t rac t aa t cac t oh t off t oho t oez t oea t dzo t dzc t cal t ral t rad t crp 0533-07 figure 7. ac waveforms for read operations
e 28f016xd flash memory 39 t rc t ras t rp t csh t rcd t cas t rsh t crp t cah t asc t rah t asr t wcs t wch t ds t dh column row t t din open ras# cas# address we# din dout oe# : don't care : don't care t wcs > _ t wcs (min) 0528_08 figure 8. ac waveforms for early write operations
28f016xd flash memory e 40 : don't care t rc t ras t rp t csh t rcd t cas t rsh t crp t cah t asc t rah t asr column row t t ras# cas# address we# din din open oe# invalid dout t cwl t rwl t wp t qeh t ds t dh t qed t clz t qez t dzc t dzo dout t rcs 0533_09 figure 9. ac waveforms for delayed write operations
e 28f016xd flash memory 41 : don't care t rwc t ras t rp t rcd t cas column row t t ras# cas# address we# t rcs din din open oe# dout dout t asr t rah t asc t cah t crp t rad t cwd t awd t rwd t cwl t rwl t wp dzc t t dh t ds rac t aa t cac t oea t oed t oeh t oho t oez t clz t dzo t 0533_10 figure 10. ac waveforms for read-modify-write operations
28f016xd flash memory e 42 row column 1 column 2 column n t t t rah t rad t asc t cah asc t cah t t asr t rcd t csh t cas t cp t cas t pc t cp t cas t rasp t cprh t crp t rp t rsh cah t asc t t cal t ral t rrh t rcs t rch t rch t rch t t dcz t dcz open open open t cdd t cdd t cdd dout 1 dout 2 dout n t dzo t oed t dzo t oed t dzo t qed t oh t oho t off t qez t rac t aa t clz t oea t cac t oez t off t oho t clz t cac t oea t oh t aa t cpa t cpa t oh t aa oho t t oez t clz t cac t oea t off ras# cas# address we# din oe# dout : don't care t cal t cal dcz 0533_11 figure 11. ac waveforms for fast page mode read operations
e 28f016xd flash memory 43 t rasp t rp ras# cas# t asr t rah t asc t cah t asc t cah t asc t cah column 1 row column 2 column n din 1 din 2 din n t wcs t wch t wcs t wch t wcs t wch t ds t dh t ds t dh t dh t ds address we# din dout oe# : don't care : don't care wcs >= t wcs (min) t t t t csh t pc t rsh t rcd t cas t cp t cas t cp t cas t rp open 0533_12 figure 12. ac waveforms for fast page mode early write operations
28f016xd flash memory e 44 t rasp t rp ras# cas# t t t csh t pc t rsh t rcd t cp column 1 row column 2 column n we# din 1 t asr t rah t cas t cas t cas t cp t rad t asc t cah t cah t cah asc asc t t t rcs t cwl t cwl t cwl t rwl t rcs t rcs t dzc din 2 din n t wp t wp t wp t ds t ds t ds t dh t dzc t dzc dh dh t dzo t dzo t dzo t oed t oed t oed t oeh t oeh t oeh t clz t oez t clz t clz t oez t oez address din oe# dout invalid dout invalid dout invalid dout : don't care 0533_13 figure 13. ac waveforms for fast page mode delayed write operations
e 28f016xd flash memory 45 t rasp t rp ras# cas# t t t rcd t cp column 1 row we# t asr t rah t cas t rad t asc t rwl din 2 din n t ds t ds t dzo t dzo t dzo t oed t clz t oez address din dout : don't care t oea t cpa column n din 2 column 2 t cas t cas t cp t prwc t crp t cah t cah t asc t asc cah t t cwl t cwl t cwl t rwd t awd t cwd t awd t awd t cwd t cwd t rcs t rcs t rcs t cpw t cpw t dzc t wp t wp t wp t ds t dzc t dh t dh t dh t dzc t oea t oea t oeh t oed t oed t oeh t oeh t cac t cac t cac t aa t aa t aa t clz t clz t oez t oez t oho t oho t oho dout 1 dout 2 dout 3 oe# 0533_14 figure 14. ac waveforms for fast page mode read-modify-write operations
28f016xd flash memory e 46 t rc t ras t rp t asr ras# cas# oe#,we# : don't care : don't care t t t rah row t off open address dout t rpc t crp 0533_15 figure 15. ac waveforms for ras#-only refresh operations
e 28f016xd flash memory 47 : don't care ras# t rc t rc t rp t rp t rp t ras t ras cas# t rpc t cp t cp t rpc t t t csr t csr t chr t chr t crp t wrp t wrh t wrp t wrh t off dout address oe#: don't care open we# 0533_16 figure 16. ac waveforms for cas#-before-ras# refresh operations
28f016xd flash memory e 48 : don't care ras# column row dout t t t asr t rah t rcd t cah t asc t chr t crp t rrh t rch t cdd t qed t qez t oho t cac t off t rc t ras t rp t rc t ras t rp t rc t ras t rp t rad t ral t aa t clz t rac t rcs t dzc t dzo t oea t oh t rsh cas# address we# din oe# dout 0533_17 figure 17. ac waveforms for hidden refresh operations
e 28f016xd flash memory 49 t ras# cas# off t rpc t cpn t csr t rass t rps t chs hi-z o n 0533_18 figure 18. ac waveforms for self-refresh operations
28f016xd flash memory e 50 5.9 power-up and reset timings rp# 3/5# 0v 3.3v v power-up cc 5.0v v cc (p) (y) (3v,5v) 4.5v plyl t t pl5v ylph t yhph t 0533_19 figure 19. v cc power-up and rp# reset waveforms symbol parameter notes min max units t plyl t plyh rp# low to 3/5# low (high) 0 s t ylph t yhph 3/5# low (high) to rp# high 0 s t pl5v t pl3v rp# low to v cc at 4.5v (minimum) rp# low to v cc at 3.0v (min) or 3.6v (max) 20 s notes: for read timings following reset, see sections 5.6 and 5.7. 1. the t ylph and/or t yhph times must be strictly followed to guarantee all other read and write specifications for the 28f016xd 2. the power supply may start to switch concurrently with rp# going low.
e 28f016xd flash memory 51 5.10 erase and word program performance (3,4) v cc = 3.3v 0.3v, v pp = 5.0v 0.5v, t a = 0c to +70c symbol parameter notes min typ (1) max units t whrh 1 word program time 2,5 tbd 35.0 tbd s t whrh 3 block program time 2,5 tbd 1.2 tbd sec block erase time 2,5 tbd 1.4 tbd sec erase suspend latency time to read 1.0 12.0 75.0 s v cc = 3.3v 0.3v, v pp = 12.0v 0.6v, t a = 0c to +70c symbol parameter notes min typ (1) max units t whrh 1 word program time 2,5 5 9 tbd s t whrh 3 block program time 2,5 tbd 0.3 1.0 sec block erase time 2 0.3 0.8 10 sec erase suspend latency time to read 1.0 9.0 55.0 s v cc = 5.0v 0.5v, v pp = 5.0v 0.5v, t a = 0c to +70c symbol parameter notes min typ (1) max units t whrh 1 word program time 2,5 tbd 25.0 tbd s t whrh 3 block program time 2,5 tbd 0.85 tbd sec block erase time 2,5 tbd 1.0 tbd sec erase suspend latency time to read 1.0 9.0 55.0 s v cc = 5.0v 0.5v, v pp = 12.0v 0.6v, t a = 0c to +70c symbol parameter notes min typ (1) max units t whrh 1 word program time 2,5 4.5 6 tbd s t whrh 3 block program time 2,5 tbd 0.2 1.0 sec block erase time 2 0.3 0.6 10 sec erase suspend latency time to read 1.0 7.0 40.0 s notes: 1. +25c, and nominal voltages. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled, but not 100% tested. guaranteed by design. 5. please contact intels application hotline or your local sales office for more information for current tbd information.
28f016xd flash memory e 52 6.0 mechanical specifications 048928.eps figure 20. mechanical specifications of the 28f016xd 56-lead tsop type i package family: thin small out-line package symbol millimeters notes minimum nominal maximum a 1.20 a 1 0.050 a 2 0.965 0.995 1.025 b 0.100 0.150 0.200 c 0.115 0.125 0.135 d 1 18.20 18.40 18.60 e 13.80 14.00 14.20 e 0.50 d 19.80 20.00 20.20 l 0.500 0.600 0.700 n56 ? 0 3 5 y 0.100 z 0.150 0.250 0.350
e 28f016xd flash memory 53 appendix a device nomenclature and ordering information product line designator for all intel flash products package e = tsop device type d = dram-interface e2 8 f 06 1 xd - 5 8 random access time (t rac ) at 5v v cc ns) device density 016 = 16 mbit product family x = fast flash 0533_21 valid combinations order code v cc = 3.3v 0.3v, 50 p f load, 1.5v i/o levels ( 1 ) v cc = 5.0v 10%, 100 pf load, ttl i/o levels ( 1 ) e28f016xd 85 E28F016XD-95 e28f016xd-85 note: 1. see section 5.3 for transient input/output reference waveforms.
28f016xd flash memory e 54 appendix b additional information (1,2) order number document/tool 297372 16-mbit flash product family users manual 292092 ap-357 power supply solutions for flash memory 292123 ap-374 flash memory write protection techniques 292126 ap-377 16-mbit flash product family software drivers, 28f016sa/sv/xd/xs 292131 ap-384 designing with the 28f016xd 292163 ap-610 flash memory in-system code and data update techniques 292168 ap-614 adapting dram based designs for the 28f016xd 292152 ab-58 28f016xd-based simm designs 292165 ab-62 compiled code optimizations for flash memories 294016 er-33 etox? flash memory technologyinsight to intels fourth generation process innovation 297508 flashbuilder utility contact intel/distribution sales office 28f016xd benchmark utility contact intel/distribution sales office flash cycling utility contact intel/distribution sales office 28f016xd ibis models contact intel/distribution sales office 28f016xd vhdl/verilog models contact intel/distribution sales office 28f016xd timingdesigner* library files contact intel/distribution sales office 28f016xd orcad and viewlogic schematic symbols note: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

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